This invention relates generally to an integrated circuit (IC) device and a method of manufacturing the IC device. More particularly, this invention relates to an IC device including one die or two or more dies arranged in a matrix array package configuration so as to achieve very high pin counts and multiple functionality with in the defined device geometry, and to a method of manufacturing such an IC device.
With the miniaturization of electronic products, there is a need to also reduce the size of IC packaged devices and to add more functionality so that more of these IC devices can be packed into a given area of a substrate. Two approaches have been taken to meet such a need. A first approach is to reduce the size of packaging of existing IC device packages. The second approach is focused on increasing the functionalities provided by each IC device, for example to form a system-in-package (SIP) devices.
FIGS. 1A- 1F show prior art IC devices fabricated in a wafer level configuration. Each individual device is packaged while they are still available in wafer form, prior to the wafer dicing process to obtain chip sized package. Many packaging process steps are added directly on a wafer to realize these chip sized packages, which are of small form factor and reduced weight, However, the IC device obtained in this method are limited to the IO density as the chip size determines the package IO density.
U.S. Pat. Nos. 6,777,267; 6,768,331; 6,667,543; 6,635,509; 6,596,560; 6,593,220; 6,465,281; 6,452,238; 6,441,488; 6,429,511; 6,341,070; 5,448,014 discloses an IC device having a footprint approximately the size of a die of the IC device. The steps for manufacturing the IC device includes: (1) providing a wafer that includes multiple dies wherein each die includes multiple connection pads, Different packaging process steps are added to arrive at the final IC device before the same are separated.